Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices), radiation-emitting devices (e.g., light-emitting diodes (LEDs), resonant cavity light-emitting diodes (RCLEDs), and vertical cavity surface-emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors). Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (30.48 cm) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is actually used to form active devices on the silicon wafer.
It has been discovered that the speed and power efficiency of semiconductor devices can be improved by electrically insulating the portion of the semiconductor material on a semiconductor substrate that is actually used to form the semiconductor devices from the remaining bulk semiconductor material of the substrate. As a result, so-called “engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively larger host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. As a result, the base substrate is often referred to in the art as a “handle” or “handling” substrate. The base substrate may also comprise a semiconductor material.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), III-V type semiconductor materials, and II-VI type semiconductor materials.
For example, an engineered substrate may include an epitaxial layer of III-V type semiconductor material formed on a surface of a base substrate such as, for example, aluminum oxide (Al2O3) (which may be referred to as “sapphire”). Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V type semiconductor material to form one or more devices on the engineered substrate.
When a layer of semiconductor material is formed (e.g., epitaxially grown) over another layer of material (e.g., an underlying layer of dielectric material or an underlying layer of a different semiconductor material) at elevated temperatures, lattice strain may be induced in the crystal lattice of the layer of semiconductor material when the resulting structure is cooled to room temperature due to any difference in the coefficients of thermal expansion (CTE) exhibited by the respective adjacent materials. If the underlying material exhibits a coefficient of thermal expansion that is higher than the coefficient of thermal expansion exhibited by the semiconductor material, the semiconductor material may be disposed in a state of compressive strain upon cooling the resulting structure. In contrast, if the underlying material exhibits a coefficient of thermal expansion that is less than the coefficient of thermal expansion exhibited by the semiconductor material, the semiconductor material may be disposed in a state of tensile strain upon cooling the resulting structure. There are various semiconductor devices and processes in which such lattice strain imposes limitations on the devices that can be fabricated.
For example, indium gallium nitride (InXGa1-XN) devices may be formed on an engineered substrate by growing one or more epitaxial device layers each comprising indium gallium nitride (InXGa1-XN) (which together form a “device structure stack”) on a seed layer of a III-nitride material (e.g., gallium nitride, indium gallium nitride) formed on the engineered substrate. Any mismatch in the crystal lattices of the adjacent layers of III-nitride materials may induce strain in the crystal lattice of one or more of the III-nitride device layers, which may effectively limit the thickness of the III-nitride device layer and/or the concentration of indium in the indium gallium nitride device layer. The presence of such lattice strain in a layer of semiconductor material may be undesirable for a number of reasons. For example, the presence of lattice strain in a layer of semiconductor material may result in an increased density of defects (e.g., lattice dislocations) in the layer of semiconductor material, undesirable morphology at the surface of the layer of semiconductor material, and may even result in the formation of cracks in the layer of semiconductor material. Furthermore, the presence of lattice strain in a layer of semiconductor material may facilitate the onset of undesirable separation of material phases within the layer of semiconductor material.
It is difficult to form an indium gallium nitride seed layer on the surface of an engineered substrate in such a manner that the indium gallium nitride seed layer has a lattice parameter that will match that of an indium gallium nitride device layer to be formed thereover. As a result, the crystal lattice of the overlying device layer of indium gallium nitride will be strained upon formation thereof using the underlying seed layer of indium gallium nitride.
In view of the above, there is a need for methods that can be used to reduce lattice parameter mismatch between adjacent layers, and the resulting lattice strain therein, in semiconductor structures and devices such as, for example, engineered substrates, integrated circuit (IC) devices, radiation-emitting devices, and radiation sensor devices.
U.S. Pat. No. 7,271,416, which issued Sep. 18, 2007 to Saxler, discloses semiconductor structures and methods of fabricating semiconductor structures for reducing strain in adjacent material layers. As disclosed therein, a semiconductor structure may include a substrate having a first in-plane unstrained lattice constant, a first layer of semiconductor material on the substrate having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant, and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer of semiconductor material. The variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate. The variable mismatch layer may be a layer having a strained in-plane lattice constant that substantially matches the unstrained lattice constant of the first layer.
U.S. patent application Ser. No. 11/237,164, which was filed Sep. 27, 2005 by Krames et al. (U.S. Patent Application Publication No. 2007/0072324 A1, published Mar. 29, 2007), now U.S. Pat. No. 8,334,155, issued Dec. 18, 2012, discloses an engineered substrate for growing a light-emitting device that includes a host substrate and a seed layer bonded to the host substrate. A semiconductor structure including a light-emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. A bonding layer may be used to bond the host substrate to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer. The host substrate may be separated from the semiconductor structure and seed layer by etching away the bonding layer.
The layers of semiconductor materials formed on engineered substrates are conventionally formed at elevated temperatures. As an engineered substrate is cooled from such elevated temperatures to room temperature, any mismatch in the coefficient of thermal expansion between adjacent layers of material in the substrate can result in lattice strain in one or both of the adjacent layers of material upon cooling of the substrate. Therefore, it would be desirable to preserve as well as possible the lattice constants of the crystal lattices of layers of material formed at a given temperature (e.g., an elevated temperature) as the temperature of the layers of material is subsequently changed (e.g., reduced to room temperature).